1. Field of the Invention
This invention relates to a semiconductor device wherein a memory cell or memory element is formed from an access transistor and a thyristor element.
2. Description of the Related Art
Various forms have been proposed for a memory cell or thyristor RAM cell formed from a thyristor element and an access transistor and are disclosed, for example, in Japanese Patent Laid-Open Nos. 2007-49113 (hereinafter referred to as Patent Document 1), 2007-67133 (hereinafter referred to as Patent Document 2) and 2002-246560 (hereinafter referred to as Patent Document 3), Rich Roy, Farid Nemati, Ken Young, Bruce Bateman, Rajesh Chopra, Seong-Ook Jung, Chiming Show, and Hyun-Jin Cho, 2006 IEEE International Solid-State Circuits Conference, pp. 632-633 (hereinafter referred to as Non-Patent Document 1), and Farid Nemati and James D. Plummer, Technical Digest IEDM 199, pp. 283-286 (hereinafter referred to as Non-Patent Document 2).
One of such memory cells as mentioned above is a memory device which includes a thyristor element and an access transistor formed on a bulk-type semiconductor substrate.
FIG. 1 is a simplified schematic cross sectional view showing an example of a configuration of a memory cell including a thyristor element and an access transistor formed on a bulk-type semiconductor substrate. The thyristor element of the memory cell is of the selective epitaxy anode (SEA) type.
Meanwhile, FIG. 2 is an equivalent circuit diagram of the memory cell of FIG. 1.
Referring to FIGS. 1 and 2, the memory element 1 shown includes a thyristor element 3 and an access transistor 4 formed in parallel to each other across an element isolation region 5 on a bulk-type semiconductor substrate 2 of the p-type.
The thyristor element 3 has a pnpn thyristor structure wherein a p-type anode 32, an n-type anode 33, a p-type base 34 and an n-type cathode 35 are formed on an n-type well 31.
A gate electrode 37 is formed on the p-type base 34 with a gate insulating film 36 interposed therebetween.
The thyristor element 3 has a combination of bipolar transistors of the npn type and the pnp type, which have a common base and a common collector. Further, the gate electrode 37 of the MIS type is formed on the base of the npn type.
The access transistor 4 includes n-type diffusion layers 42 and 43 formed in a p-type well 41, and a gate electrode 45 formed on the p-type well 41 sandwiched between the diffusion layers 42 and 43 with a gate insulating film 44 interposed therebetween.
The p-type anode 32 of the thyristor element 3 is connected to a supply line LVREF of a reference voltage Vref, and the diffusion layer 42 of the access transistor 4 is connected to a bit line BL while the n-type cathode 35 of the thyristor element 3 and the diffusion layer 43 of the access transistor 4 are connected to each other by a storage node VSN.
The gate electrode 37 of the thyristor element 3 is connected to a word line TWL, and the gate electrode 45 of the access transistor 4 is connected to another word line SWL.
The thyristor element having such a configuration as described above has a negative resistance characteristic and has two stable points. The two stable points are read as 0 and 1 of data.
In the following, the voltage or potential state of a thyristor RAM cell upon operation is described.
FIGS. 3A and 3B illustrate a potential state when the thyristor RAM cell retains data.
When the thyristor RAM cell retains data, the word lines SWL and TWL are set to 0 V, that is, to an off state, and also the bit line is set to 0 V as seen in FIG. 3A.
At this time, as seen in FIG. 3B, a stable point at which thyristor current It and access transistor current Ia balance with each other is given only by two states, and the two stable states are allocated to “0” and “1” of data to store or retain data.
FIGS. 4A and 4B illustrate a potential state upon data reading out operation of the thyristor RAM cell.
Upon reading out operation of the thyristor RAM cell, the word line TWL is set to 0 V while the word line SWL is set to a power supply voltage VDD and the bit line BL is precharged to 0 V as seen in FIG. 4A.
At this time, while a stable point in the retaining state is maintained, the current value changes at the stable point, and consequently, data reading out operation can be carried out by reading out the current value.
FIGS. 5A and 5B illustrate a potential state upon data writing operation of the thyristor RAM cell.
Upon writing operation of data “1” during which the cell current is high, the word line TWL is set to the power supply voltage VDD and also the word line SWL is set to the power supply voltage VDD while the bit line BL is set to 0 V as seen in FIG. 5A.
In this potential state, since only one stable state in which the cell current is high is provided as seen in FIG. 5B, data “1” can be written.
FIGS. 6A and 6B illustrate a potential state upon writing operation of data “0” into the thyristor RAM cell.
Upon writing operation of data “0” during which the cell current is low, the word line TWL is set to the power supply voltage VDD and also the word line SWL is set to the power supply voltage VDD while the bit line BL is set to the power supply voltage VDD as seen in FIG. 6A.
In this potential state, since only one stable state in which the cell current is low is provided as seen in FIG. 6B, data “0” can be written.